1. Field of the Invention
The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and an apparatus for speeding up program execution by continuing to speculatively execute instructions in scout mode using a parallel speculative thread after a stall condition has cleared and the main thread resumes normal execution.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
Efficient caching schemes can help reduce the number of memory accesses that are performed. However, when a memory reference, such as a load operation, generates a cache miss, the subsequent access to level-two (L2) cache or memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.
A number of techniques are presently used (or have been proposed) to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster. Moreover, constraints on the number of physical registers that are available for register renaming purposes during out-of-order execution also limits the effective size of the issue queue.
Some designers have proposed entering a scout mode when a stall condition is encountered. During scout mode, the processor speculatively executes instructions to prefetch future loads, but the processor does not commit the results to the architectural state of the processor. For example, see U.S. patent application Ser. No. 10/741,944, entitled “Generating Prefetches by Speculatively Executing Code Through Hardware Scout Threading,” by inventors Shailender Chaudhry and Marc Tremblay. This solution to the latency problem eliminates the complexity of the issue queue and the rename unit, and also achieves memory-level parallelism.
Note that after the stall condition is cleared, the processor leaves scout mode and returns to normal-execution mode. However, performance can be lost if the processor leaves scout mode just before executing an instruction which would have generated a useful prefetch. For example, suppose a processor executing in normal-execution mode encounters a stall condition which causes the processor to enter scout mode, wherein instructions are speculatively executed by a speculative thread to prefetch future loads, but results are not committed to the architectural state of the processor. At some time in the future, when the stall condition clears, the processor will return to normal-execution mode. If the processor is just about to generate a useful prefetch when it returns to normal-execution mode, the processor can potentially lose the opportunity to hide the memory latency for the useful prefetch because the processor returns to normal-execution mode instead of prefetching a cache line that it will eventually need.
Hence, what is needed is a method and an apparatus that facilitates prefetching cache lines during stall conditions without the above-described drawbacks of existing processor designs that support scout mode.